THE F-LDPC FAMILY A Highly Flexible FEC Solution Offering Universally Good Performance and High Speed Decoding White Paper

The introduction of turbo codes and the rediscovery of low-density parity-check (LDPC) codes have revolutionized coding theory and practice. Such modern codes offer outstanding coding gain over traditional (e.g., algebraic or convolutional) codes – more than 3 dB in many cases. While good modern codes have been demonstrated for most operational scenarios of interest, no one simple code structure has been shown to simultaneously provide good performance and low hardware implementation complexity over the entire range of practical interest. Moreover, the use of a modern code designed for a specific operating scenario outside of its limited " comfort zone " often leads to degraded performance or significantly increased implementation complexity. Modern code designs to date have thus lacked the flexibility demanded in today's communication and storage systems. In this white paper, we introduce TrellisWare's Flexible Low-Density Parity-Check (F-LDPC) code family. The F-LDPC family can achieve excellent performance across an extraordinary range of code rates and block sizes with a design that is especially amenable to low-complexity, high-throughput hardware implementation. Table 1 summarizes the key features of the F-LDPC family and compares them to that of existing modern codes: Table 1: F-LDPC feature summary and comparison www.trellisware.com 2 fair good best fair Parallelism good fair fair best poor For desired flexibility poor fair fair good For desired throughput good best Complexity: best fair good Threshold poor good Floor/flare poor fair good fair good Performance: good Block size poor poor best good poor fair fair Code rate best poor Flexibility: TPC LDPC SCCC PCCC F-LDPC